Memory circuits are well known, and include an array of memory cells, each capable of storing a bit of information. In order to appropriately access a desired word of information, comprising a plurality of bits, appropriate row decoder circuits are used which select appropriate row lines (or word lines) for access. Similarly, column accessing circuitry is often employed to select an appropriate number of bits within the for output.
FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to the prior art. In FIG. 1, the nonvolatile semiconductor memory device 1 consists of a memory cell array 10 having a plurality of memory cells MCxy (x=0, 1, 2, . . . , i and y=0, 1, 2, . . . , j), a plurality of word lines WLx, and a plurality of bit lines BLy. Each of the memory cells MCxy is an electrically erasable and programmable read only memory ("EEPROM") cell (or flash EEPROM cell) or an electrically programmable read only memory ("EPROM") cell, and has a control gate, a floating gate, a source, and a drain. Their control gates are coupled respectively to corresponding word lines WLx, their drains are tied to corresponding bit lines BLy, and their sources are grounded. The nonvolatile semiconductor memory device of such a memory cell arrangement structure is often referred to as "NOR structured flash memory device".
As illustrated in FIG. 1, the nonvolatile semiconductor memory device 1 further comprises a row decoder circuit 20, which selects one of the word lines WLx and drives the selected word line with a word line voltage Vpp (for example, reading, programming, erasing, or verification voltage) required at each mode of operation. The row decoder circuit 20 has a plurality of word line drivers 22 each connected to corresponding word lines WLx. Each of the word line drivers 22 drives a corresponding word line WLx with the word line voltage Vpp in response to a corresponding selection signal (DRAx), for example, a signal decoded by a row address decoding circuit (not shown). One of the bit lines BLy is selected by a column pass gating circuit 30, which, for example, consists of switching transistors (not shown) switched on/off by corresponding column selection signals Y0-Yj, respectively. A column decoder circuit 40 selects one of lines 43 to transfer corresponding column selection signals Y0-Yj, and has a plurality of column drivers 42. Each of the column drivers 42 drives the corresponding line 43 with a voltage required for each mode of operation.
Referring to FIG. 2, a detailed circuit diagram of a word line driver 22 connected to one word line (for example, WL0) according to the first prior art is illustrated, but those of other word line drivers 22 connected respectively to word lines (for example, WL1-WLi) are the same as that of the word line driver 22. The word line driver 22 has three input nodes 30, 31, and 32 receiving a selection signal DRAi, a word line voltage Vpp, and a shut off signal Shut.sub.-- Off, respectively. The word line driver 22 consists of an invertor 33, two PMOS transistors 34 and 35, and two NMOS transistors 36 and 37 connected as shown in FIG. 2.
The operation of the word line driver 22 associated with program and read modes of operation will be described below.
First, a read operation for a selected memory cell MC00 is described. During the read operation, a word line voltage Vpp of about +4.5 volts is applied to the word line WL0 connected to the word line driver 22, and a bit line voltage of about +1 volts is supplied to a bit line BL0 connected to the selected memory cell MC00. At this time, the selection signal DRA0 becomes a `H` level (for example, the level has a power supply voltage Vcc level) and the shut off signal Shut.sub.-- Off has the `H` level. Under this condition, a node ND1 becomes a `L` level (for example, a ground voltage level) through the invertor 33, and a node ND2 has the `L` level through the NMOS transistor 36 switched on by the shut off signal Shut.sub.-- Off. This turns off the NMOS transistor 37 and turns on the PMOS transistor 35, so that the word line WL0 is pulled up to the word line voltage Vpp of about +4.5 volts through the PMOS transistor 35 thus turned on.
During the program operation, the word line voltage Vpp of about +10 volts is applied to the word line WL0 and a bit line voltage of about +5 volts is supplied to the bit line BL0. At this time, the selection signal DRA0 and the shut off signal Shut.sub.-- Off both are at the `H` level. Under this condition, the node ND1 becomes the `L` level through the invertor 33, and the node ND2 has the `L` level through the NMOS transistor 36 switched on by the shut off signal Shut.sub.-- Off. This turns off the NMOS transistor 37 and turns on the PMOS transistor 35, so that the word line WL0 is pulled up to the word line voltage Vpp of about +10 volts through the PMOS transistor 35.
As is well-known in the art, the program/erase mode of operation is performed, and then a verification operation for the program/erase mode of operation is performed to detect whether a selected memory cell is programmed at a required threshold voltage (for example, 6-8 volts) or is erased at a required threshold voltage (for example, 1-3 volts). In general, in a nonvolatile semiconductor memory device having NOR structured flash memories, an over-erasure verification voltage applied to a word line is about +1 volts and an erasure verification voltage applied thereto is about +3 volts.
During an over-erasure verification operation in which a voltage Vpp of about +1 volts is applied to a selected word line (for example, WL0), a selection signal DRA0 and the shut off signal Shut.sub.-- Off are both at the `H` level. This turns on the PMOS transistor 35 through the NMOS transistor 36, switched on by the shut off signal Shut.sub.-- Off, and turns off the NMOS transistor 37, so that the word line WL0 is pulled up to the voltage of about +1 volt.
Simultaneously, a ground voltage is applied to deselected word lines WL1-WLi, and selection signals DRA1-DRAi associated with the deselected word lines WL1-WLi are at the `L` level. Under this condition, the node ND1 has the `H` level and the NMOS transistor 37 is turned on. This forces each deselected word line WL1-WLi to be grounded, and then the PMOS transistor 34 in each driver 22 is turned on. The node ND2 is pulled up to the voltage Vpp of about +1 volts through the PMOS transistor 34. As a result, the nodes ND1 and ND2 are shorted through the NMOS transistor 36, turned on by the shut off signal having the `H` level, enabling the word line voltage Vpp applied to the selected word line WL0 to be raised in voltage toward Vcc. That is, one problem in the prior art is that the word line driver 22 in FIG. 2 does not transfer the word line voltage Vpp into the corresponding word line when the word line voltage Vpp is less than a power supply voltage Vcc.
Referring to FIG. 3, a second prior art detailed circuit diagram of a word line driver 22 is shown. In that circuit, when a selection signal DRAi is at the `L` level and the word line voltage Vpp is at about +1 volt (or when the word line voltage Vpp is less than a power supply voltage Vcc), a node ND3 becomes the `H` level through both an invertor 38 and an NMOS transistor 39 turned on by the shut off signal Shut.sub.-- Off. A deselected word line WLi is grounded through the NMOS transistor 40, and then a PMOS transistor 41 is turned on, again shorting the node ND3 and Vpp. Therefore, the word line driver 22 in FIG. 3 has the same problem as that in FIG. 2.